Accelerating NoC Verification Using a Complete Model and Active Window
نویسندگان
چکیده
This work presents formal modeling of Network-on-Chip (NoC) considering detailed functional units NoC. The intricate NoC router components like buffer, switch, and arbiter is accomplished using Finite State Machine (FSM). As in the case a real NoC, parallel execution these carried out by maintaining synchronization between within each adjacent routers presented model. Important properties for correctness proposed model are verified checker. Implementing complete memory extensive operation while verifying with We have introduced concept active windows to verify its communication routers. checked routers, progress units, successful transfer packets. Verification starvation freedom an also performed round-robin fixed-priority arbiter. Parallel threads used experiments reduce verification time.
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ژورنال
عنوان ژورنال: IEEE Access
سال: 2022
ISSN: ['2169-3536']
DOI: https://doi.org/10.1109/access.2022.3199671